The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of improving address access time (tAA) characteristics which denote a quality factor showing how fast data are outputted on inputting of a read command, and determines performance of the semiconductor memory device.
FIG. 1 is a block diagram of a conventional semiconductor memory device having first to eighth banks.
As the storage capacity of semiconductor memory devices have increased and the use of high performance memory devices such as double duty rate III (DDR3) dynamic random access memory (DRAM) devices have become more popular, semiconductor memory devices have changed from a four-bank structure to an eight-bank structure. In semiconductor memory devices, a part corresponding to a data input/output pad is called a “DQ pad” and a part corresponding to an address and command input/output pad is called an “AC pad”.
As shown in FIG. 1, a plurality of DQ pads are located together at one side of a chip, and a plurality of AC pads are located together at another side of the chip. Herein, the first to eighth banks are distant from or close to the DQ pads according to their positions, and the first to eighth banks are also distant from or close to the AC pads according to their positions. As shown, the sixth bank BANK5 and the eighth bank BANK7 are grouped together with reference symbols “DQ WORST CMD BEST” and are distant from the DQ pads but close to the AC pads. In addition, the first bank BANK0 and the third bank BANK2 are grouped together with reference symbols “DQ BEST CMD WORST” and are distant from the AC pads but close to the DQ pads.
FIG. 2 is a timing diagram illustrating a write operation of the first to eighth banks.
In detail, an upper portion of the timing diagram shows a write operation of the banks grouped as “DQ WORST CMD BEST” in fast process, voltage and temperature (PVT) conditions. A lower portion of the timing diagram shows a write operation of the banks grouped as “DQ BEST CMD WORST” in slow PVT conditions. Herein, fast PVT conditions, where the process is fast, the voltage is high and the temperature is low, correspond to good tAA characteristics, where the tAA characteristics denote a quality factor showing how fast data are outputted on inputting of a read command. Further, slow PVT conditions, where the process is slow, the voltage is low and the temperature is high, correspond to bad tAA characteristics.
Data to be written to the banks (hereinafter, referring to as “write data”) are transferred from the DQ pads to the banks, and written to the banks in response to a bank enable signal BWEN. The write data are written to a memory cell at a column side in response to a column selection signal YS which is selected based on a column address. The column selection signal YS may be enabled at substantially the same time as an activation of the bank enable signal BWEN with a short time delay. Further, the column selection signal YS is delayed or advanced accordingly as the bank enable signal BWEN is advanced or delayed.
In general, as the write data transferred to the banks are intended to have the least delay time, the number of logic gates passed through by the write data is designed to be minimized. The write data are merely transferred to the banks via a long metal line, e.g., a global input/output (GIO) line. The GIO line may have the characteristic of an RC delay and a little variation between fast PVT conditions and slow PVT conditions. The GIO line is classified as a data-group transmission line, and thus the write data transferred via the GIO line are classified as a data-group signal. A time margin “tGIO” shown in FIG. 2 denotes a time difference caused by PVT variation of the data-group signal.
On the contrary, the bank enable signal BWEN and the column selection signal YS, which are inputted to address and command input/output pads, i.e., the pads AC PADs shown in FIG. 1, and transferred to banks, i.e., the banks BANK 1-7 shown in FIG. 1, vary sensitively according to PVT conditions because they pass through a relatively large number of logic gates, e.g., a timing controlling circuit and other controllers, which are classified as a command-group transmission line between the pads AC PADs and the banks BANK 1-7. Such signals as the bank enable signal BWEN and the column selection signal YS are classified as command-group signals. A time margin “tCMD” shown in FIG. 2 denotes a time difference caused by PVT variation of a command-group signal. Herein, the time margin “tCMD” is larger than the time margin “tGIO”.
It is required that data-group signals such as the write data reach the banks prior to command-group signals such as the bank enable signal BWEN and the column selection signal YS, for guaranteeing the timing margin “tMARGIN” shown in FIG. 2. However, the command-group signal varies sensitively according to the PVT conditions, and thus, the command-group signal is faster than the data-group signal in fast PVT conditions. Because of this, sometimes the timing margin “tMARGIN” cannot be guaranteed. Accordingly, it is required that the command-group signal may be delayed for a predetermined time by design. In particular, in the case of the banks grouped as “DQ WORST” and “CMD BEST” as shown in the upper portion of the timing diagram of FIG. 2, it is necessary for the command-group signals such as the bank enable signal BWEN and the column selection signal YS to be delayed.
The lower portion of the timing diagram shown in FIG. 2 shows the write operation of the banks grouped as “DQ BEST CMD WORST” in slow PVT conditions. In such conditions, the command-group signals such as the bank enable signal BWEN and the column selection signal YS are transferred very slowly to the banks, but data-group signals such as the write data are transferred to the banks relatively faster than the command-group signals. This is because the data-group signals are transferred to the banks located at “DQ BEST CMD WORST” and varies insensitively according to the PVT conditions, while the command-group signals are transferred to the banks located at “DO BEST CMD WORST” and delayed for the predetermined time by design for guaranteeing the timing margin “tMARGIN” in the fast PVT conditions.
In a read operation as well as a write operation, the column selection signal YS is enabled so that read data are transferred to the GIO line from the banks. At this time, the tAA characteristics increase because the column selection signal YS is delayed as described above. The tAA characteristics mean a quality factor showing how fast the read data are outputted from inputting of a read command to thereby determine performance of the semiconductor memory device.